The present invention relates to a wiring method for automatically determining a wiring route between cells using a computer in a polycell style semiconductor integrated circuit device.
In a polycell style semiconductor integrated circuit device, a circuit having a logic or memory function is normally constituted by a region, known as a circuit cell (to be hereinafter referred to simply as a cell), rectangular in shape and of uniform height. The cells are arranged in line, without gaps therebetween, to constitute a cell row. A plurality of cell rows are arranged on a chip, and terminals of the cells are connected via a wiring segment, thus realizing a desired circuit operation. A cell has a pattern designed in advance, e.g., NAND, NOR, flip-flop, or the like. Using this wiring method, a complicated and large-scale circuit system can be relatively easily realized as a semiconductor integrated circuit device.
In a normal polycell style semiconductor integrated circuit chip, a plurality of cell rows are aligned on the chip, and wiring regions are formed between adjacent cell rows. Arranged around the chip is an I/O circuit region. The wiring regions, i.e., the channel regions, serve as interconnection regions for interconnecting the I/O terminals of the cells. The interconnections normally employ two metal interconnection layers, and different layers are assigned in the horizontal and vertical directions. The area of each channel region is not always predetermined, but is normally determined by the number of tracks required for interconnections after completion of the wiring operation.
Normally, each cell row includes portions through which metal conductors of the second layer can pass. Wiring which must extend over a plurality of cell rows (wiring passing through such a wiring route is called "feed-through wiring") is carried out across the cells through which the metal wiring layer can pass. When the number of cells through which the metal wiring layer can pass is few as compared to the number of wiring routes requiring the feed-through wiring, a feed-through cell is used, and the feed-through wiring is performed across the cell.
When, in the polycell style semiconductor integrated circuit device as described above, a wiring layout is determined by automatic wiring using a computer, the area of the wiring region must be minimized, as must also the lengths of wiring lines. A typical known wiring method is the channel wiring method, wherein a wiring region is divided into a plurality of channels, and the wiring layout is determined for each channel. The channel wiring method allows high-speed processing using a computer, and can achieve an almost 100% wiring ratio.
In the case of the conventional channel wiring method, the wiring direction of terminals is selected for each of the nets (groups of terminals to be connected to an identical potential). In this case, it is selected if a wiring segment from a terminal of interest is connected to an adjacent channel in a cell row on which the cell of interest is present, or if the wiring segment is connected to an adjacent channel below the cell of interest, or if the wiring segment is connected to both the channels. Upon computer processing for the above selection, the presence/absence of a wiring inhibition region in a cell, reduction of a wiring region, and the like are taken into account. Nets (nets requiring the feed-through wiring) which must extend over a cell row are sequentially extracted in a given order, and positions on a cell row through which the wiring segment passes are determined for the extracted net. Using this method, the general wiring route of the net requiring the feed-through wiring is also determined, at the same time. General wiring is also called "global wiring". After completion of the global wiring, the channel wiring operation is then sequentially executed for each channel.
Since, by using this method, feed-through cell assignment for the feed-through wiring and channel assignment, for determining the wiring route, is sequentially determined for each net requiring the feed-through wiring in the global wiring operation, these assignments cannot be synthetically determined for all the channels, with the result that the degree of concentration of the wiring segments varies from channel to channel. Consequently, the channel area is undesirably increased, and the degree of integration cannot be improved to the degree desired. More specifically, since the nets are sequentially processed, the feed-through cell of the currently processed net and a channel for the wiring route are determined on the basis of the cells or channels previously assigned for the feed-through wiring and wiring route. For this reason, it is not easy to optimally assign the cells and channels for the feed-through wiring and wiring route. In the sequential processing, the order of wiring routes for those nets requiring the feed-through wiring influences the resultant wiring state. More specifically, cells or channels assigned to the feed-through wiring or wiring route of each net are changed, depending on the extraction order of nets requiring the feed-through wiring. As a result, the total number of wiring segments used for the wiring of each channel after completion of channel wiring may be changed. Therefore, the height of a wiring region and the area of the chip are likely to change, depending on the order by which nets require the feed-through wiring. Thus, it is very difficult to optimally assign the feed-through cells or channels.
As has been described above, when using the conventional global wiring method in relation to the polycell style semiconductor integrated circuit device, it is difficult to optimize the assignment of the feed-through cell and channels for determining the wiring route for nets requiring through-wiring. As a result, the area of the wiring region is likely to be increased, so that the degree of integration of the chip cannot be improved to a sufficiently satisfactory degree.